590 search results - page 5 / 118 » A Novel Method to Improve the Test Efficiency of VLSI Tests |
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
Reducing power dissipation and testing time is accomplished by forming two clusters of don’t-care bit inside an input and a response test cube. New reordering scheme of scan lat...
IOLTS
2005
IEEE
14 years 1 months ago
2005
IEEE
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...
DATE
1999
IEEE
13 years 11 months ago
1999
IEEE
In this paper we propose an efficient transient test generation method to comprehensively test analog circuits using minimum test time. A divide and conquer strategy is formulated...
DFT
2002
IEEE
14 years 13 days ago
2002
IEEE
This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test v...
DFT
2005
IEEE
13 years 9 months ago
2005
IEEE
Linear decompressors are the dominant methodology used in commercial test data compression tools. However, they are generally not able to exploit correlations in the test data, an...