130 search results - page 9 / 26 » A Novel Metric for Interconnect Architecture Performance |
MICRO
2007
IEEE
14 years 2 months ago
2007
IEEE
The performance of computer systems varies over the course of their execution. A system may perform well during some parts of its execution and poorly during others. To understand...
FPGA
2008
ACM
13 years 9 months ago
2008
ACM
A design tool for routing channel segmentation in islandstyle FPGAs is presented. Given the FPGA architecture parameters and a set of benchmark designs, the tool optimizes routing...
DAC
1996
ACM
14 years 1 days ago
1996
ACM
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
Rising interconnect delay and power consumption have motivated the investigation of alternative integrated circuit routing architectures. In particular, the X Architecture, which ...
ERSA
2009
13 years 5 months ago
2009
We present the architecture and programming model for MORA, a coarse-grained reconfigurable processor aimed at multimedia applications. The MORA architecure is a MIMD machine consi...