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FCCM
2006
IEEE
106views VLSI» more  FCCM 2006»
14 years 1 months ago
Scalable Hardware Architecture for Real-Time Dynamic Programming Applications
Abstract— This paper introduces a novel architecture for performing the core computations required by dynamic programming (DP) techniques. The latter pertain to a vast range of a...
Brad Matthews, Itamar Elhanany
ISCA
1998
IEEE
135views Hardware» more  ISCA 1998»
13 years 11 months ago
Branch Prediction Based on Universal Data Compression Algorithms
Data compression and prediction are closely related. Thus prediction methods based on data compression algorithms have been suggested for the branch prediction problem. In this wo...
Eitan Federovsky, Meir Feder, Shlomo Weiss
ASAP
2007
IEEE
203views Hardware» more  ASAP 2007»
13 years 11 months ago
Reconfigurable Universal Adder
In this paper we present a novel adder/subtracter arithmetic unit that combines Binary and Binary Code Decimal (BCD) operations. The proposed unit uses effective addition/subtract...
Humberto Calderon, Georgi Gaydadjiev, Stamatis Vas...
EH
2005
IEEE
123views Hardware» more  EH 2005»
14 years 1 months ago
Embryonic Machines That Grow, Self-Replicate and Self-Repair
After a reminder about embryonic machines endowed with universal construction and universal computation properties, this paper presents a novel architecture providing additional s...
André Stauffer, Daniel Mange, Gianluca Temp...
ASPDAC
2010
ACM
161views Hardware» more  ASPDAC 2010»
13 years 4 months ago
Novel dual-Vth independent-gate FinFET circuits
This paper describes gate work function and oxide thickness tuning to realize novel circuits using dual-Vth independent-gate FinFETs. Dual-Vth FinFETs with independent gates enabl...
Masoud Rostami, Kartik Mohanram