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» A Parallel Packet Screen for High Speed Networks
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ICC
2009
IEEE
106views Communications» more  ICC 2009»
14 years 3 months ago
Distributed ECN-Based Congestion Control
—Following the design philosophy of XCP, VCP is a router-assisted congestion protocol that intends to balance the efficiency and the fairness control in high Bandwidth-Delay Pro...
Xiaolong Li, Homayoun Yousefi'zadeh
RECONFIG
2009
IEEE
269views VLSI» more  RECONFIG 2009»
14 years 3 months ago
A 10 Gbps OTN Framer Implementation Targeting FPGA Devices
Abstract—Integrated circuits for very high-speed telecommunication protocols often use ASICs, due to their strict timing constraints. This scenario is changing, since modern FPGA...
Guilherme Guindani, Frederico Ferlini, Jeferson Ol...
MICRO
2010
IEEE
130views Hardware» more  MICRO 2010»
13 years 6 months ago
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
Minseon Ahn, Eun Jung Kim
SIGMETRICS
2008
ACM
181views Hardware» more  SIGMETRICS 2008»
13 years 8 months ago
Counter braids: a novel counter architecture for per-flow measurement
Fine-grained network measurement requires routers and switches to update large arrays of counters at very high link speed (e.g. 40 Gbps). A naive algorithm needs an infeasible amo...
Yi Lu, Andrea Montanari, Balaji Prabhakar, Sarang ...
3DIC
2009
IEEE
263views Hardware» more  3DIC 2009»
14 years 2 days ago
3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC)
Abstract— Networks-on-chip (NoC) is emerging as a key onchip communication architecture for multiprocessor systemson-chip (MPSoC). In traditional electronic NoCs, high bandwidth ...
Yaoyao Ye, Lian Duan, Jiang Xu, Jin Ouyang, Mo Kwa...