31 search results - page 3 / 7 » A Parallel and Modular Architecture for 802.16e LDPC Codes |
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
— The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and ...
SIPS
2008
IEEE
14 years 2 months ago
2008
IEEE
Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon li...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
Abstract— We analyze the decoding algorithm for regular timeinvariant LDPC convolutional codes as a 3D signal processing scheme and derive several parallelization concepts, which...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
— A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row m...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
A massively scalable architecture for decoding low-density parity-check codes is presented in this paper. This novel architecture uses hardware scaling and memory partitioning to ...