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» A Scalable Architecture for Maximizing Concurrency
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ICCD
2008
IEEE
420views Hardware» more  ICCD 2008»
14 years 5 months ago
Frequency and voltage planning for multi-core processors under thermal constraints
— Clock frequency and transistor density increases have resulted in elevated chip temperatures. In order to meet temperature constraints while still exploiting the performance op...
Michael Kadin, Sherief Reda
DATE
2010
IEEE
113views Hardware» more  DATE 2010»
14 years 1 months ago
PM-COSYN: PE and memory co-synthesis for MPSoCs
—Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory...
Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang
DAC
2010
ACM
14 years 14 days ago
A parallel integer programming approach to global routing
We propose a parallel global routing algorithm that concurrently processes routing subproblems corresponding to rectangular subregions covering the chip area. The algorithm uses a...
Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth
ISLPED
2005
ACM
178views Hardware» more  ISLPED 2005»
14 years 2 months ago
Energy efficient strategies for deployment of a two-level wireless sensor network
We investigate and develop energy-efficient strategies for deployment of wireless sensor networks (WSN) for the purpose of monitoring some phenomenon of interest in a coverage reg...
Ali Iranli, Morteza Maleki, Massoud Pedram
AUSAI
2005
Springer
14 years 2 months ago
Adaptive Utility-Based Scheduling in Resource-Constrained Systems
This paper addresses the problem of scheduling jobs in soft real-time systems, where the utility of completing each job decreases over time. We present a utility-based framework fo...
David Vengerov