294 search results - page 1 / 59 » A System Level Resource Estimation Tool for FPGAs |
FPL
2004
Springer
14 years 4 months ago
2004
Springer
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...
ICCD
2001
IEEE
14 years 7 months ago
2001
IEEE
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
TCAD
2011
13 years 5 months ago
2011
—Escalating system-on-chip design complexity is the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early...
TVLSI
2010
13 years 5 months ago
2010
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
ICCD
2006
IEEE
14 years 7 months ago
2006
IEEE
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chi...