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» A System Level Resource Estimation Tool for FPGAs
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ECTEL
2007
Springer
14 years 5 months ago
Learning Resource Referencing, Search and Aggregation at the eLearning System Level
TELOS is a new eLearning system being built within the Canadian LORNET project. TELOS aims to provide an open operating system in which users can develop and use eLearning and know...
Gilbert Paquette, François Magnan
LCTRTS
2009
Springer
14 years 5 months ago
Debugging FPGA-based packet processing systems through transaction-level communication-centric monitoring
The fine-grained parallelism inherent in FPGAs has encouraged their use in packet processing systems. Debugging and performance evaluation of such complex designs can be signifi...
Paul Edward McKechnie, Michaela Blott, Wim Vanderb...
DAC
1994
ACM
14 years 2 months ago
Performance-Driven Simultaneous Place and Route for Row-Based FPGAs
Sequential place and route tools for FPGAs are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty in predicting these ...
Sudip Nag, Rob A. Rutenbar
DAC
2002
ACM
14 years 11 months ago
IP delivery for FPGAs using Applets and JHDL
This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain F...
Michael J. Wirthlin, Brian McMurtrey
DAC
2006
ACM
14 years 11 months ago
Transistor abstraction for the functional verification of FPGAs
or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdu...
Guy Dupenloup, Thierry Lemeunier, Roland Mayr