209 search results - page 33 / 42 » A Systematic Approach for Designing Testable VLSI Circuits |
GLVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
In dense integrated circuit designs, management of routing congestion is essential; an over congested design may be unroutable. Many factors influence congestion: placement, rout...
DT
2000
13 years 7 months ago
2000
Effective high-level ATPG tools are increasingly needed, as an essential element in the quest for reducing as much as possible the designer work on gate-level descriptions. We pro...
ISPD
2009
ACM
14 years 2 months ago
2009
ACM
Gate sizing and threshold voltage (Vt) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven h...
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for oor...
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...