209 search results - page 38 / 42 » A Systematic Approach for Designing Testable VLSI Circuits |
ISPD
2010
ACM
14 years 2 months ago
2010
ACM
This paper presents SafeChoice (SC), a novel clustering algorithm for wirelength-driven placement. Unlike all previous approaches, SC is proposed based on a fundamental theorem, s...
ISLPED
2003
ACM
14 years 29 days ago
2003
ACM
A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes would be promising approaches for futu...
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
— In today’s VLSI designs, there can be many blockages in a routing region. The obstacle-avoiding rectilinear Steiner minimum tree (OARSMT) problem has become an important prob...
TODAES
2002
13 years 7 months ago
2002
ct Cross-coupled noise analysis has become a critical concern in today's VLSI designs. Typically, noise analysis makes an assumption that all aggressing nets can simultaneousl...
ISPD
1999
ACM
14 years 22 hour ago
1999
ACM
Buffer insertion is an effective approach to achieve both minimal clock signal delay and skew in high speed VLSI circuit design. In this paper, we develop an optimal buffer ins...