209 search results - page 5 / 42 » A Systematic Approach for Designing Testable VLSI Circuits |
IJON
2006
13 years 7 months ago
2006
: In this paper we present a complete neuromorphic image processing system and we report the development of an integrated CMOS low-power circuit to test the feasibility of its diff...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper describes a DfT solution for modern seriallink transceivers. We first summarize the architectures of the Crosstalk Canceller and the Equalizer used in advanced transcei...
GLVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
- A current-mode logic (CML) buffer is based on a simple differential circuit. This paper investigates important problems involved in the design of a CML buffer as well as a chain ...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
ATS
1996
IEEE
13 years 12 months ago
1996
IEEE
In this paper, we present a novel and efticient approach to test MCM at the module as well as chip levels. Our design incorporates the concept of the multifrequency test method an...