60 search results - page 5 / 12 » A Test Point Insertion Algorithm for Mixed-Signal Circuits |
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
This paper accurately considers wire short defects and proposes an algorithm to guarantee IC chip yield rate improvement for redundant wire insertion. Without considering yield ra...
HASE
2008
IEEE
13 years 7 months ago
2008
IEEE
In this paper, we propose a randomization based technique to verify whether a manufactured chip conforms to its design or is infected by any trojan circuit. A trojan circuit can be...
ATS
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
FPL
2004
Springer
14 years 26 days ago
2004
Springer
Abstract. We present an evaluation of accelerating fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is fre...
ITC
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...