11 search results - page 1 / 3 » A Two-Level Load Store Queue Based on Execution Locality |
ISCA
2008
IEEE
14 years 2 months ago
2008
IEEE
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents NoSQ (short for No Store Queue), a microarchitecture that performs store-load communication without a store queue and without executing stores in the outof-ord...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
The load-store unit is a performance critical component of a dynamically-scheduled processor. It is also a complex and non-scalable component. Several recently proposed techniques...
MICRO
2000
IEEE
14 years 2 days ago
2000
IEEE
Silent store instructions write values that exactly match the values that are already stored at the memory address that is being written. A recent study reveals that significant ...
CAL
2010
13 years 4 months ago
2010
Memory models like SC, TSO, and PC enforce load-load ordering, requiring that loads from any single thread appear to occur in program order to all other threads. Out-of-order execu...