Sciweavers

2695 search results - page 34 / 539
» A Visual Approach to Validating System Level Designs
Sort
View
SEW
2006
IEEE
14 years 2 months ago
Retrenching the Purse: Finite Exception Logs, and Validating the Small
The Mondex Electronic Purse is an outstanding example of industrial scale formal refinement, and was the first verification to achieve ITSEC level E6 certification. A formal a...
Richard Banach, Michael Poppleton, Susan Stepney
ISLPED
2003
ACM
80views Hardware» more  ISLPED 2003»
14 years 2 months ago
Level conversion for dual-supply systems
Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter (LC) im...
Fujio Ishihara, Farhana Sheikh, Borivoje Nikolic
DAC
2004
ACM
14 years 2 months ago
Extending the transaction level modeling approach for fast communication architecture exploration
System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems....
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
ICRA
2002
IEEE
166views Robotics» more  ICRA 2002»
14 years 1 months ago
A Decoupled Image Space Approach to Visual Servo Control of a Robotic Manipulator
An image-based visual servo control is presented for a robotic manipulator. The proposed control design addresses visual servo of 'eye-in-hand' type systems. Using a nov...
Robert E. Mahony, Tarek Hamel, François Cha...
DAC
1997
ACM
14 years 1 months ago
System-Level Synthesis of Low-Power Hard Real-Time Systems
We present a system-level approach for power optimization under a set of user specified costs and timing constraints of hard real-time designs. The approach optimizes all three d...
Darko Kirovski, Miodrag Potkonjak