Sciweavers

2695 search results - page 48 / 539
» A Visual Approach to Validating System Level Designs
Sort
View
DAC
2006
ACM
14 years 2 months ago
Use of C/C++ models for architecture exploration and verification of DSPs
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
David Brier, Raj S. Mitra
CVPR
2006
IEEE
14 years 11 months ago
The Design of High-Level Features for Photo Quality Assessment
1 We propose a principled method for designing high level features for photo quality assessment. Our resulting system can classify between high quality professional photos and low...
Yan Ke, Xiaoou Tang, Feng Jing
HPCA
2008
IEEE
14 years 3 months ago
Speculative instruction validation for performance-reliability trade-off
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
DATE
2004
IEEE
152views Hardware» more  DATE 2004»
14 years 19 days ago
A Design Methodology for the Exploitation of High Level Communication Synthesis
In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In par...
Francesco Bruschi, Massimo Bombana
MM
2006
ACM
125views Multimedia» more  MM 2006»
14 years 2 months ago
The design of a real-time, multimodal biofeedback system for stroke patient rehabilitation
This paper presents a novel real-time, multi-modal biofeedback system for stroke patient therapy. The problem is important as traditional mechanisms of rehabilitation are monotono...
Yinpeng Chen, He Huang, Weiwei Xu, Richard Isaac W...