228 search results - page 10 / 46 » A bipartition-codec architecture to reduce power in pipeline... |
ISLPED
1995
ACM
14 years 3 days ago
1995
ACM
A dual-rail CMOS adiabatic switching circuit approach is described which follows the electroid model of Hall. These circuits can operate in either the retractile cascade or the re...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
—Increasing power density causes die overheating due to limited cooling capacity of the package. Conventional thermal management techniques e.g. logic shutdown, clock gating, fre...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
GLVLSI
2005
IEEE
14 years 2 months ago
2005
IEEE
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
—In this paper we study the effectiveness of two power gating methods – transistor switches and MEMS switches – in reducing the power consumption of a design with a certain t...