228 search results - page 25 / 46 » A bipartition-codec architecture to reduce power in pipeline... |
FPGA
2009
ACM
14 years 3 months ago
2009
ACM
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
VLSID
2005
IEEE
14 years 9 months ago
2005
IEEE
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
DAC
2004
ACM
14 years 9 months ago
2004
ACM
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
DATE
2004
IEEE
14 years 10 days ago
2004
IEEE
: Static energy dissipation in cache memories will constitute an increasingly larger portion of total microprocessor energy dissipation due to nanoscale technology characteristics ...
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
To achieve minimum signal propagation delay, the nonuniform wire width routing architecture has been widely used in modern VLSI design. The non-uniform routing architecture exploi...