228 search results - page 40 / 46 » A bipartition-codec architecture to reduce power in pipeline... |
TC
2010
13 years 8 months ago
2010
—Due to the widespread use and inherent complexity of floating-point addition, much effort has been devoted to its speedup via algorithmic and circuit techniques. We propose a ne...
DAC
2009
ACM
14 years 10 months ago
2009
ACM
Three-dimensional integrated circuits (3D ICs) offer a promising solution to overcome the on-chip communication bottleneck and improve performance over traditional two-dimensional...
DAC
2011
ACM
12 years 9 months ago
2011
ACM
Existing thermal-aware 3D placement methods assume that the temperature of 3D ICs can be optimized by properly distributing the power dissipations, and ignoring the heat conductiv...
DAC
2006
ACM
14 years 10 months ago
2006
ACM
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
DAC
2005
ACM
14 years 10 months ago
2005
ACM
We present a new methodology which takes into consideration the effect of Within-Die (WID) process variations on a low-voltage parallel system. We show that in the presence of pro...