121 search results - page 17 / 25 » A cell-based power estimation in CMOS combinational circuits |
ISCAS
2002
IEEE
14 years 11 days ago
2002
IEEE
A novel charge-based comparator and folding circuit are presented. Correlated double sampling comparison is performed using a log-domain integrator, implemented by a subthreshold ...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
ISQED
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract — Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and sig...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...
ISLPED
2010
ACM
13 years 7 months ago
2010
ACM
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...