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» A code compression advisory tool for embedded processors
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CSREAESA
2006
13 years 9 months ago
Static Program Partitioning for Embedded Processors
Modern processors have a small on-chip local memory for instructions. Usually it is in the form of a cache but in some cases it is an addressable memory. In the latter, the user is...
Bageshri Sathe, Uday P. Khedker
CODES
2006
IEEE
13 years 9 months ago
Architectural support for safe software execution on embedded processors
The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and mo...
Divya Arora, Anand Raghunathan, Srivaths Ravi, Nir...
CASES
2007
ACM
13 years 11 months ago
Fragment cache management for dynamic binary translators in embedded systems with scratchpad
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...
José Baiocchi, Bruce R. Childers, Jack W. D...
CODES
2005
IEEE
14 years 1 months ago
Comparing the size of .NET applications with native code
Byte-code based languages are slowly becoming adopted in embedded domains because of improved security and portability. Another potential reason for their adoption is the reputati...
Roberto Costa, Erven Rohou
FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
14 years 1 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski