31 search results - page 4 / 7 » A configuration memory hierarchy for fast reconfiguration wi... |
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Multi-context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant ove...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
Embedded system programs tend to spend much time in small loops. Introducing a very small loop cache into the instruction memory hierarchy has thus been shown to substantially red...
TVLSI
2010
13 years 2 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
APNOMS
2008
Springer
13 years 9 months ago
2008
Springer
Abstract. Wireless sensor network is a suitable technology for ubiquitous environment. However, in WSN, as the network size grows larger, overheads such as flooding, calculation an...
FPL
2009
Springer
14 years 6 days ago
2009
Springer
Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Acce...