129 search results - page 11 / 26 » A datapath synthesis system for the reconfigurable datapath ... |
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper, we propose a methodology for partitioning and mapping computational intensive applications in reconfigurable hardware blocks of different granularity. A generic hyb...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
: Common sub-expression elimination (CSE) serves as a useful optimization technique in the synthesis of arithmetic datapaths described at RTL. However, CSE has a limited potential ...
DATE
1999
IEEE
13 years 11 months ago
1999
IEEE
Previous work has shown that sizable power reductions can be achieved by shutting down a system's sub-circuits when they are not needed. However, these shutdown techniques fo...
ISQED
2008
IEEE
14 years 1 months ago
2008
IEEE
In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimiza...
ISSS
1996
IEEE
13 years 11 months ago
1996
IEEE
An address generation and optimization environment (ADOPT) for distributed memory architectures, is presented. ADOPT is oriented to minimize the area overhead introduced by the us...