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ARITH
2007
IEEE
13 years 11 months ago
Robust Energy-Efficient Adder Topologies
In this paper we explore the relationship between adder topology and energy efficiency. We compare the energy-delay tradeoff curves of selected 32-bit adder topologies, to determi...
Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, R...
CASES
2003
ACM
13 years 11 months ago
A hierarchical approach for energy efficient application design using heterogeneous embedded systems
Several features such as reconfiguration, voltage and frequency scaling, low-power operating states, duty-cycling, etc. are exploited for latency and energy efficient application ...
Sumit Mohanty, Viktor K. Prasanna
USENIX
2008
13 years 10 months ago
Cutting Corners: Workbench Automation for Server Benchmarking
A common approach to benchmarking a server is to measure its behavior under load from a workload generator. Often a set of such experiments is required-perhaps with different serv...
Piyush Shivam, Varun Marupadi, Jeffrey S. Chase, T...
DAC
2004
ACM
14 years 1 months ago
Extending the transaction level modeling approach for fast communication architecture exploration
System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems....
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
DATE
1999
IEEE
147views Hardware» more  DATE 1999»
13 years 12 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi