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» A design platform for 90-nm leakage reduction techniques
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HPCA
2011
IEEE
12 years 11 months ago
Archipelago: A polymorphic cache design for enabling robust near-threshold operation
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
ISCAS
2007
IEEE
90views Hardware» more  ISCAS 2007»
14 years 1 months ago
Leakage-Aware Design of Nanometer SoC
– In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be simultaneously suppressed for effective energy reduction. New low-leakage circu...
Volkan Kursun, Sherif A. Tawfik, Zhiyu Liu
ASAP
2009
IEEE
119views Hardware» more  ASAP 2009»
13 years 11 months ago
A Low Power High Performance Radix-4 Approximate Squaring Circuit
An implementation of a radix-4 approximate squaring circuit is described employing a new operand dual recoding technique. Approximate squaring circuits have numerous applications ...
Satyendra R. Datla, Mitchell A. Thornton, David W....
GLVLSI
2007
IEEE
114views VLSI» more  GLVLSI 2007»
14 years 2 months ago
Design of mixed gates for leakage reduction
Leakage power dissipation is one of the most critical factors for the overall current dissipation and future designs. However, design techniques for the reduction of leakage power...
Frank Sill, Jiaxi You, Dirk Timmermann
PATMOS
2004
Springer
14 years 1 months ago
Sleepy Stack Reduction of Leakage Power
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as...
Jun-Cheol Park, Vincent John Mooney III, Philipp P...