102 search results - page 8 / 21 » A design platform for 90-nm leakage reduction techniques |
GLVLSI
2008
IEEE
14 years 2 months ago
2008
IEEE
Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
DSD
2008
IEEE
13 years 9 months ago
2008
IEEE
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay techniques. We discovered that a filter cache, traditionally used for reducing...
EMSOFT
2005
Springer
14 years 1 months ago
2005
Springer
Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts have tried to integrate architecture...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source...
TCAD
2010
13 years 2 months ago
2010
Starting from the 90nm technology node, process induced stress has played a key role in the design of highperformance devices. The emergence of source/drain silicon germanium (S/D ...