6 search results - page 1 / 2 » A dual-MST approach for clock network synthesis |
ASPDAC
2010
ACM
13 years 9 months ago
2010
ACM
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
DAC
2008
ACM
14 years 12 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
DAC
2005
ACM
14 years 24 days ago
2005
ACM
Although a lot of research efforts have been made in the minimization of the total power consumption caused by the clock tree, no attention has been paid to the minimization of th...
ICCAD
2010
IEEE
13 years 8 months ago
2010
IEEE
Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthe...
DATE
2007
IEEE
14 years 5 months ago
2007
IEEE
Design closure becomes hard to achieve at physical layout stage due to the emergence of long global interconnects. Consequently, interconnect planning needs to be integrated in hi...