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DATE
2003
IEEE
116views Hardware» more  DATE 2003»
14 years 19 days ago
Statistical Timing Analysis Using Bounds
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing anal...
Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sar...
DAC
2004
ACM
13 years 11 months ago
Statistical gate delay model considering multiple input switching
There is an increased dominance of intra-die process variations, creating a need for an accurate and fast statistical timing analysis. Most of the recent proposed approaches assum...
Aseem Agarwal, Florentin Dartu, David Blaauw
TCAD
2008
98views more  TCAD 2008»
13 years 7 months ago
Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models
Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timin...
Khaled R. Heloue, Farid N. Najm
ICCAD
2005
IEEE
133views Hardware» more  ICCAD 2005»
14 years 4 months ago
Gate sizing using incremental parameterized statistical timing analysis
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
Matthew R. Guthaus, Natesan Venkateswaran, Chandu ...
VLSID
2005
IEEE
150views VLSI» more  VLSID 2005»
14 years 7 months ago
Multivariate Normal Distribution Based Statistical Timing Analysis Using Global Projection and Local Expansion
This paper employs general multivariate normal distribution to develop a new efficient statistical timing analysis methodology. The paper presents the theoretical framework of the...
Baohua Wang, Pinaki Mazumder