Sciweavers

1013 search results - page 184 / 203
» A hardware implementation of realloc function
Sort
View
DATE
2007
IEEE
173views Hardware» more  DATE 2007»
14 years 2 months ago
Architectural leakage-aware management of partitioned scratchpad memories
Partitioning a memory into multiple blocks that can be independently accessed is a widely used technique to reduce its dynamic power. For embedded systems, its benefits can be ev...
Olga Golubeva, Mirko Loghi, Massimo Poncino, Enric...
MICRO
2007
IEEE
150views Hardware» more  MICRO 2007»
14 years 2 months ago
Leveraging 3D Technology for Improved Reliability
Aggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower sup...
Niti Madan, Rajeev Balasubramonian
MICRO
2007
IEEE
168views Hardware» more  MICRO 2007»
14 years 2 months ago
Global Multi-Threaded Instruction Scheduling
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
Guilherme Ottoni, David I. August
IWMM
2007
Springer
116views Hardware» more  IWMM 2007»
14 years 2 months ago
Heap space analysis for java bytecode
This article presents a heap space analysis for (sequential) Java bytecode. The analysis generates heap space cost relations which define at compile-time the heap consumption of ...
Elvira Albert, Samir Genaim, Miguel Gómez-Z...
DATE
2006
IEEE
123views Hardware» more  DATE 2006»
14 years 2 months ago
Networks on chips for high-end consumer-electronics TV system architectures
Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SO...
Frits Steenhof, Harry Duque, Björn Nilsson, K...