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ARC
2008
Springer
104views Hardware» more  ARC 2008»
13 years 9 months ago
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
Frank Hannig, Holger Ruckdeschel, Hritam Dutta, J&...
ASAP
2009
IEEE
159views Hardware» more  ASAP 2009»
14 years 2 months ago
A High-Performance Hardware Architecture for Spectral Hash Algorithm
—The Spectral Hash algorithm is one of the Round 1 candidates for the SHA-3 family, and is based on spectral arithmetic over a finite field, involving multidimensional discrete...
Ray C. C. Cheung, Çetin K. Koç, John...
DATE
2005
IEEE
113views Hardware» more  DATE 2005»
14 years 1 months ago
Hardware-Software Design of a Smart Sensor for Fully-Electronic DNA Hybridization Detection
This paper describes the design of a smart sensor for label-free detection of DNA hybridization. The sensor is based on a direct electrical transduction principle: it measures imp...
Claudio Stagni, Carlotta Guiducci, Massimo Lanzoni...
FPL
1999
Springer
103views Hardware» more  FPL 1999»
14 years 2 days ago
IP Validation for FPGAs Using Hardware Object Technology
Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional ...
Steve Casselman, John Schewel, Christophe Beaumont
VIP
2001
13 years 9 months ago
High-speed Parameterisable Hough Transform Using Reconfigurable Hardware
Recent developments in reconfigurable hardware technologies have offered high-density high-speed devices with the ability for custom computing whilst maintaining the flexibility o...
Dixon D. S. Deng, Hossam A. ElGindy