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ASYNC
2004
IEEE
107views Hardware» more  ASYNC 2004»
13 years 11 months ago
A Fast and Energy-Efficient Stack
We present some novel hardware implementations of a stack. All designs are clockless, fast, and energy efficient, while occupying modest area. We implemented a 42-place stack chip...
Jo C. Ebergen, Daniel Finchelstein, Russell Kao, J...
FPL
2007
Springer
125views Hardware» more  FPL 2007»
14 years 2 months ago
Run-time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II-Pro
Reconfigurable computing entails the utilization of a generalpurpose processor augmented with a reconfigurable hardware structure (usually an FPGA). Normally, a complete recon...
Stefan Raaijmakers, Stephan Wong
ASAP
2008
IEEE
93views Hardware» more  ASAP 2008»
14 years 2 months ago
Memory copies in multi-level memory systems
Data movement operations, such as the C-style memcpy function, are often used to duplicate or communicate data. This type of function typically produces a significant amount of o...
Pepijn J. de Langen, Ben H. H. Juurlink
ICES
1998
Springer
131views Hardware» more  ICES 1998»
14 years 3 days ago
Aspects of Digital Evolution: Geometry and Learning
In this paper we present a new chromosome representation for evolving digital circuits. The representation is based very closely on the chip architecture of the Xilinx 6216 FPGA. W...
Julian F. Miller, Peter Thomson
ISSS
1995
IEEE
117views Hardware» more  ISSS 1995»
13 years 11 months ago
Scheduling and resource binding for low power
Decisions taken at the earliest steps of the design process may have a significantimpact on the characteristics of the final implementation. This paper illustrates how power con...
Enric Musoll, Jordi Cortadella