172 search results - page 20 / 35 » A high performance reconfigurable Motion Estimation hardware... |
ISCAS
1995
IEEE
13 years 11 months ago
1995
IEEE
Abstract -- Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel field programmab...
ISLPED
2003
ACM
14 years 23 days ago
2003
ACM
High performance processors use checkpointing to rapidly recover from branch mispredictions and possibly other exceptions. We demonstrate that conventional checkpointing becomes u...
DATE
2003
IEEE
14 years 24 days ago
2003
IEEE
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
IEEECIT
2010
IEEE
13 years 6 months ago
2010
IEEE
- The increase of embedded applications complexity has demanded hardware more flexible while providing higher performance. Reconfigurable architectures and stream processing have b...