159 search results - page 14 / 32 » A high throughput 3D-bus interconnect for network processors |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory a...
ISCAS
2008
IEEE
14 years 1 months ago
2008
IEEE
— By using self-assembling fabrication techniques at the cellular, molecular, or atomic scale, it is nowadays possible to create functional assemblies in a mainly bottom-up way t...
GLOBECOM
2008
IEEE
14 years 1 months ago
2008
IEEE
To achieve Terabit and Petabit switching, both time (high transmission speed) and space (multi-stage interconnection network) technologies are required. We propose an Ethernet for...
PDP
2010
IEEE
13 years 11 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
NOCS
2009
IEEE
14 years 2 months ago
2009
IEEE
Future manycore processors will require energyefficient, high-throughput on-chip networks. Siliconphotonics is a promising new interconnect technology which offers lower power, h...