90 search results - page 7 / 18 » A low power FPGA routing architecture |
VLSID
2006
IEEE
14 years 7 months ago
2006
IEEE
A low power multilevel interconnect architecture that uses wave-pipelined multiplexed (WPM) interconnect routing is proposed in this paper. WPM takes advantage of existing interco...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Process induced threshold voltage variations bring about fluctuations in circuit delay, that affect the FPGA timing yield. We propose an adaptive FPGA architecture that compensate...
TVLSI
2008
13 years 7 months ago
2008
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
FPL
2008
Springer
13 years 9 months ago
2008
Springer
Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within ...
SLIP
2009
ACM
14 years 1 months ago
2009
ACM
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...