16 search results - page 2 / 4 » A low-leakage current power 180-nm CMOS SRAM |
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
— Reducing the leakage power in embedded SRAM memories is critical for low-power applications. Raising the source voltage of SRAM cells in standby mode reduces the leakage curren...
JCP
2008
13 years 8 months ago
2008
Semiconductor manufacturing process scaling increases leakage and transistor variations, both of which are problematic for static random access memory (SRAM). Since SRAM is a criti...
ISQED
2006
IEEE
14 years 2 months ago
2006
IEEE
- A low overhead circuit technique is proposed in this paper for simultaneously reducing subthreshold and gate oxide leakage currents in domino logic circuits. PMOS sleep transisto...
ASPDAC
2009
ACM
14 years 1 months ago
2009
ACM
— In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise pro...
VLSI
2005
Springer
14 years 2 months ago
2005
Springer
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption a...