11 search results - page 2 / 3 » A methodology for mapping multiple use-cases onto networks o... |
IPMU
2010
Springer
13 years 6 months ago
2010
Springer
In this paper we extend a methodology for constructing a frame of discernment from belief functions for one problem, into a methodology for constructing multiple frames of discernm...
VLSID
2010
IEEE
13 years 11 months ago
2010
IEEE
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
VLSID
2004
IEEE
14 years 8 months ago
2004
IEEE
As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts...
ISNN
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. Artificial Neural Networks (ANNs) and image processing requires massively parallel computation of simple operator accompanied by heavy memory access. Thus, this type of ...
CODES
2002
IEEE
14 years 21 days ago
2002
IEEE
High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power ef...