76 search results - page 2 / 16 » A methodology to improve timing yield in the presence of pro... |
ASPDAC
2009
ACM
14 years 1 months ago
2009
ACM
—Considering process variability at the behavior synthesis level is necessary, because it makes some instances of function units slower and others faster, resulting in unbalanced...
DAC
2010
ACM
13 years 7 months ago
2010
ACM
With technology scaling down to 90nm and below, many yield-driven design and optimization methodologies have been proposed to cope with the prominent process variation and to incr...
VLSID
2007
IEEE
14 years 7 months ago
2007
IEEE
As technology scales to 40nm and beyond, intra-die process variability will cause large delay and leakage variations across a chip in addition to expected die-to-die variations. I...
TCAD
2008
13 years 7 months ago
2008
Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timin...
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...