76 search results - page 4 / 16 » A methodology to improve timing yield in the presence of pro... |
DAC
2007
ACM
14 years 8 months ago
2007
ACM
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
DATE
2003
IEEE
14 years 23 days ago
2003
IEEE
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Process variation has become a critical problem in modern VLSI fabrication. In the presence of process variation, buffer insertion problem under performance constraints becomes mo...
GLVLSI
2010
IEEE
14 years 17 days ago
2010
IEEE
A methodology is proposed for designing robust circuits exhibiting higher tolerance to process and environmental variations. This higher tolerance is achieved by exploiting the in...
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
Errors caused by tolerance variations and mismatches among components severely degrade the performance of integrated circuits. These random effects in process parameters significa...