28 search results - page 3 / 6 » A multi-level static memory cell |
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
- Data in conventional six transistor (6T) static random access memory (SRAM) cells are vulnerable to noise due to the direct access to the data storage nodes through the bit lines...
SOCC
2008
IEEE
14 years 2 months ago
2008
IEEE
— Lowering supply voltage is an effective technique for power reduction in memory design, however traditional memory cell design fails to operate, as shown in [3], [10], at ultra...
POPL
1998
ACM
13 years 12 months ago
1998
ACM
Memory expansions are classical means to extract parallelism from imperative programs. However, for dynamic control programs with general memory accesses, such transformations eit...
GLVLSI
2008
IEEE
14 years 2 months ago
2008
IEEE
This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it i...
DATE
2010
IEEE
14 years 22 days ago
2010
IEEE
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...