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» A multiple clocking scheme for low power RTL design
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MICRO
2003
IEEE
143views Hardware» more  MICRO 2003»
14 years 22 days ago
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
Energy-efficient processor design is becoming more and more important with technology scaling and with high performance requirements. Supply-voltage scaling is an efficient way to...
Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik ...
GLVLSI
2003
IEEE
152views VLSI» more  GLVLSI 2003»
14 years 23 days ago
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
Frank Grassert, Dirk Timmermann
PATMOS
2000
Springer
13 years 11 months ago
Dynamic Memory Design for Low Data-Retention Power
Abstract. The emergence of data-intensive applications in mobile environments has resulted in portable electronic systems with increasingly large dynamic memories. The typical oper...
Joohee Kim, Marios C. Papaefthymiou
GLOBECOM
2008
IEEE
14 years 1 months ago
A Low-Signalling Scheme for Distributed Resource Allocation in Multi-Cellular OFDMA Systems
—This paper considers distributed protocol design for joint sub-carrier, transmission scheduling and power management in uplink/downlink multi-cellular OFDMA wireless networks. T...
Pablo Soldati, Mikael Johansson
GLVLSI
2009
IEEE
123views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Power efficient tree-based crosslinks for skew reduction
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutio...
Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G...