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HPCA
2008
IEEE
14 years 8 months ago
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often ...
Jiang Lin, Qingda Lu, Xiaoning Ding, Zhao Zhang, X...
CG
2008
Springer
13 years 7 months ago
Parallel techniques for physically based simulation on multi-core processor architectures
As multi-core processor systems become more and more widespread, the demand for efficient parallel algorithms also propagates into the field of computer graphics. This is especial...
Bernhard Thomaszewski, Simon Pabst, Wolfgang Bloch...
HASE
1998
IEEE
13 years 12 months ago
Combining Various Solution Techniques for Dynamic Fault Tree Analysis of Computer Systems
Fault trees provide a graphical and logical framework for analyzing the reliability of systems. A fault tree provides a conceptually simple modeling framework to represent the sys...
Ragavan Manian, Joanne Bechta Dugan, David Coppit,...
ITC
2003
IEEE
167views Hardware» more  ITC 2003»
14 years 27 days ago
Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of...
Rahul Kundu, R. D. (Shawn) Blanton
VLSID
2004
IEEE
147views VLSI» more  VLSID 2004»
14 years 8 months ago
Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
Shabbir H. Batterywala, Narendra V. Shenoy