155 search results - page 18 / 31 » A new heuristic algorithm for reversible logic synthesis |
ASYNC
2001
IEEE
13 years 11 months ago
2001
IEEE
This paper presents a new approach to two-level hazardfree sum-of-products logic minimization. No currently available minimizers for single-output literal-exact two-level hazard-f...
CCE
2005
13 years 7 months ago
2005
Process network problems can be formulated as Generalized Disjunctive Programs where a logicbased representation is used to deal with the discrete and continuous decisions. A new ...
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
ISPD
2012
ACM
12 years 3 months ago
2012
ACM
In this paper, we propose a new approach for gated bus synthesis [16] with minimum wire capacitance per transaction in three-dimensional (3D) ICs. The 3D IC technology connects di...