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» A non-scan DFT method at register-transfer level to achieve ...
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ASPDAC
2000
ACM
82views Hardware» more  ASPDAC 2000»
13 years 11 months ago
A non-scan DFT method at register-transfer level to achieve complete fault efficiency
Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa, ...
DFT
1999
IEEE
125views VLSI» more  DFT 1999»
13 years 11 months ago
Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures
The inherent redundancy and in-the-field reconfiguration capabilities of field programmable gate arrays (FPGAs) provide alternatives to integrated circuit redundancy-based fault r...
John Lach, William H. Mangione-Smith, Miodrag Potk...
ICCD
2006
IEEE
105views Hardware» more  ICCD 2006»
14 years 1 months ago
A New Class of Sequential Circuits with Acyclic Test Generation Complexity
—This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but whose t...
Chia Yee Ooi, Hideo Fujiwara
DDECS
2007
IEEE
201views Hardware» more  DDECS 2007»
14 years 1 months ago
Built in Defect Prognosis for Embedded Memories
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskaran...