121 search results - page 12 / 25 » A novel deadlock avoidance algorithm and its hardware implem... |
TVLSI
2010
13 years 2 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents a novel approach for multiprocess synthesis supporting well-tailored module integration at system level. The goal is to extend the local scope of existing arch...
ICCD
2003
IEEE
14 years 4 months ago
2003
IEEE
Functional symmetries provide significant benefits for multiple tasks in synthesis and verification. Many applications require the manual specification of symmetries using spe...
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
— The emergence of multi-core and many-core processors has introduced new opportunities and challenges to EDA research and development. While the availability of increasing paral...
ISCAS
2003
IEEE
14 years 28 days ago
2003
IEEE
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...