252 search results - page 7 / 51 » A novel high throughput reconfigurable FPGA architecture |
ARC
2008
Springer
13 years 9 months ago
2008
Springer
Abstract. This paper presents a novel dynamically reconfigurable hardware architecture for lossless compression and its optimization for space imagery. The proposed system makes us...
FCCM
2008
IEEE
14 years 2 months ago
2008
IEEE
Internet Protocol (IP) lookup in routers can be implemented by some form of tree traversal. Pipelining can dramatically improve the search throughput. However, it results in unbal...
NOCS
2007
IEEE
14 years 1 months ago
2007
IEEE
We present a novel network-on-chip-based architecture for future programmable chips (FPGAs). A key challenge for FPGA design is supporting numerous highly variable design instance...
CLEIEJ
2010
13 years 5 months ago
2010
This work presents a dedicated hardware design for the Forward Quantization Module (Q module) of the H.264/AVC Video Coding Standard, using optimized multipliers. The goal of this...
DELTA
2008
IEEE
14 years 2 months ago
2008
IEEE
Efficient generation of random and pseudorandom sequences is of great importance to a number of applications [4]. In this paper, an efficient implementation of the Mersenne Twis...