26 search results - page 3 / 6 » A novel scan architecture for power-efficient, rapid test |
MTDT
2002
IEEE
14 years 1 months ago
2002
IEEE
The amount of memory being embedded on chip is growing rapidly. This strongly implies that memory Built-in-self-test (BIST) logic assumes utmost importance amongst all on chip sel...
DAC
1999
ACM
14 years 25 days ago
1999
ACM
As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests which can be run at native speeds is becoming a serious proble...
EUROGRAPHICS
2010
Eurographics
14 years 4 months ago
2010
Eurographics
We present a novel approach to ray tracing execution on commodity graphics hardware using CUDA. We decompose
a standard ray tracing algorithm into several data-parallel stages tha...
DDECS
2007
IEEE
14 years 2 months ago
2007
IEEE
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...