17 search results - page 3 / 4 » A parallel IEEE P754 decimal floating-point multiplier |
DSD
2003
IEEE
14 years 19 days ago
2003
IEEE
Double precision floating-point arithmetic is inadequate for many scientific computations. This paper presents the design of a quadruple precision floating-point multiplier tha...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
The IEEE P754 Draft Standard for Floating-point Arithmetic provides specifications for Decimal Floating-Point (DFP) formats and operations. Based on this standard, many developer...
ARITH
2007
IEEE
14 years 1 months ago
2007
IEEE
The floating-point multiply-add fused (MAF) unit sets a new trend in the processor design to speed up floatingpoint performance in scientific and multimedia applications. This ...
ASAP
2003
IEEE
14 years 19 days ago
2003
IEEE
Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This p...
ARITH
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry–save multioperand addition that us...