420 search results - page 37 / 84 » A pseudo-hierarchical methodology for high performance micro... |
DAC
1999
ACM
14 years 29 days ago
1999
ACM
High performance circuit techniques such as domino logic have migrated from the microprocessor world into more mainstream ASIC designs. The problem is that domino logic comes at a...
HPCA
2008
IEEE
14 years 3 months ago
2008
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
VLSID
2002
IEEE
14 years 9 months ago
2002
IEEE
Abstract - The deep sub-micron regime has broughtup several manufacturing issues which impact circuit-performance and design. One such issue is flaring of transistors which causes ...
IPPS
2008
IEEE
14 years 3 months ago
2008
IEEE
We present an auto-tuning approach to optimize application performance on emerging multicore architectures. The methodology extends the idea of searchbased performance optimizatio...
GLVLSI
2007
IEEE
14 years 3 months ago
2007
IEEE
Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides...