Sciweavers

359 search results - page 34 / 72
» A section cache system designed for VLIW architectures
Sort
View
SAC
2006
ACM
14 years 1 months ago
Hardware/software 2D-3D backprojection on a SoPC platform
The reduction of image reconstruction time is needed to spread the use of PET for research and routine clinical practice. In this purpose, this article presents a hardware/softwar...
Nicolas Gac, Stéphane Mancini, Michel Desvi...
CODES
2007
IEEE
14 years 2 months ago
A data protection unit for NoC-based architectures
Security is gaining increasing relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses the security aspects related...
Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic...
GLVLSI
2010
IEEE
187views VLSI» more  GLVLSI 2010»
14 years 15 days ago
Write activity reduction on flash main memory via smart victim cache
Flash Memory is a desirable candidate for main memory replacement in embedded systems due to its low leakage power consumption, higher density and non-volatility characteristics. ...
Liang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Ts...
FCCM
2000
IEEE
105views VLSI» more  FCCM 2000»
14 years 2 days ago
Configuration Relocation and Defragmentation for Reconfigurable Computing
Custom computing systems exhibit significant speedups over traditional microprocessors by mapping compute-intensive sections of a program to reconfigurable logic [Hauck98]. Howeve...
Katherine Compton, James Cooley, Stephen Knol, Sco...
LCTRTS
2009
Springer
14 years 2 months ago
Addressing the challenges of DBT for the ARM architecture
Dynamic binary translation (DBT) can provide security, virtualization, resource management and other desirable services to embedded systems. Although DBT has many benefits, its r...
Ryan W. Moore, José Baiocchi, Bruce R. Chil...