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ICCAD
2004
IEEE
134views Hardware» more  ICCAD 2004»
14 years 4 months ago
An analytic placer for mixed-size placement and timing-driven placement
We extend the APlace wirelength-driven standard-cell analytic placement framework of [21] to address timing-driven and mixedsize (“boulders and dust”) placement. Compared with...
Andrew B. Kahng, Qinke Wang
SLIP
2005
ACM
14 years 1 months ago
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool
The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing in...
Young-Su Kwon, Payam Lajevardi, Anantha P. Chandra...
DAC
1998
ACM
14 years 8 months ago
Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts?
Commercial tools for standard-cell based datapath design are here classed according to design flows, and the advantages of each class are discussed with the results of two test ci...
Alexander Grießing, Paolo Ienne
ICCD
2002
IEEE
107views Hardware» more  ICCD 2002»
14 years 4 months ago
A Standard-Cell Placement Tool for Designs with High Row Utilization
Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh
ICCAD
2001
IEEE
103views Hardware» more  ICCAD 2001»
14 years 4 months ago
Interconnect Resource-Aware Placement for Hierarchical FPGAs
In this paper, we utilize Rent’s rule as an empirical measure for efficient clustering and placement of circuits on hierarchical FPGAs. We show that careful matching of design c...
Amit Singh, Ganapathy Parthasarathy, Malgorzata Ma...