214 search results - page 16 / 43 » A system level design methodology for the optimization of he... |
IJES
2008
13 years 7 months ago
2008
: On-chipimplementationofmultiprocessorsystemsneedstoplanarisetheinterconnect networks onto the silicon floorplan. Compared with traditional ASIC/SoC architectures, Multiprocessor ...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Partitioning is a time consuming and computationally complex optimization problem in the codesign of hardware software systems. The stringent time-to-market requirements have resu...
DATE
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper presents a new approach to cross-level hierarchical high-level synthesis. A methodology is presented, that supports the efficient synthesis of hierarchical specified sy...
FPL
2004
Springer
13 years 11 months ago
2004
Springer
A recent trend towards integrating FPGAs with many heterogeneous components, such as memory systems, dedicated multipliers, etc., has made them an attractive option for implementin...
HPCA
2003
IEEE
14 years 8 months ago
2003
IEEE
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...